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  • Location:Home>Research>Research Programs
    Designing Quad-Core Loongson-3 Processor
    Update time: 2009-09-10
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    Name of Project: Designing Quad-Core Loongson-3 Processor
    Source of Project: Key project supported by 863 Program advanced by the Ministry of Science and Technology 
    Person in Charge: Hu Weiwu

    Project Profile:
      The target of the project is to develop high performance computer, server and high end desktop application oriented quad-core Loongson general purpose CPU chip (hereinafter referred to as Loongson-3) and prototype system, with a basic frequency of 1.0GHz, power consumption lower than 15 watts, and production cost within USD 100. The SPEC CPU2000 value and the SPEC CPU2000 rate value of the prototype shall reach 550 and exceed 25 respectively. Besides, in the project, the quad-core general purpose chip developed by ICT will be used as computational node in “High Performance Computer and Grid Service Environment”, a key project under 863 Program.
      Loongson-3 adopts 65nm technology in its design. The main specifications of the chip and prototype are as follows:(1)64-digit 4-issue core, the main frequency of each core being above 1GHz;(2)4 processor cores, 4MB level 2 Cache, 2 DDR2 memory controllers, 1-2 HT high speed IO controller and other necessary interface logic are integrated in the chip; (3)EEC check or odd-even check is realized for the major data path to enhance its reliability; (4)Based on actual measurement, the highest power consumption upon full-load running of the chip is lower than 15 watts; (5)The cost for chip production after mass production is not higher than USD 100;(6)The SPEC CPU2000 value of the prototype system under 1-core running reaches 550, and the SPEC CPU2000 Rate value under 4-core running is above 25.

    Major scope of research covers the following:
    (1)Architecture and Logic Design
      Loongson-3 adopts adjustable 2-dimensional mesh interconnection structure, with an 8*8 crossbar connecting the 4 processors and four-individual-processor shared Level 2 Cache at each node, and the node is connected with other nodes in 4 directions. The Level 2 Cache in the chip of Loognson-3 is located in different nodes, and is shared by all processors. By supporting the major features of X86 instruction system, Loognson-3 enables high-efficiency translation from X86 program to MIPS program and it is compatible with X86. 
    (2)Design for Test
      The Design for Test of Loongson-3 includes design for full scan test of standard unit logic, BIST test of RAM unit, JTAG test of PAD, function test via Scan Collar, redundancy design for the RAM of Level 2 Cache, and redundancy design of RAM of Level 2 Cache, and so on.
    (3)Function Verification
      The Function verification of Loognson-3 includes function verification of the core of the processor, module level simulation, all-system simulation, FPGA verification on partial scale, and so on. 
    (4)Physical Design
      Loongson-3 will adopt 65nm technology in its design. Fully customized design module includes multi-port register file, CAM module, phy used for HT and high speed IO, etc. IP based design and hierarchical design are applied in combination to simplify the physical design of Loognson-3.
    (5)Prototype System Design
      The prototype system design involves hardware design and software design. Hardware design includes the verification of system main board and prototype main board; while the software design includes transplanting and developing BIOS, operation system, virtual machine, etc. 


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