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    Research on Digital VLSI Testing Techniques
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    Update time: 2009-08-19
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    NSFC Key Project: Research on Digital VLSI Testing Techniques
    Grant No. 60633060
    PI: Professor LI Xiaowei
    Abstract:
    Facing the challenges on VLSI testing which caused by the continual effect of Moore's law on integrated circuits, this key project will study test technology and methodology of digital VLSI circuits, especially for multi-core microprocessor. To cope with the most critical problem of multi-core microprocessor testing, which could be described as "how to provide high quality test for multi-core microprocessor with multi-clock domains". This key project will focus on the following five topics: (1) automatic test pattern generation methods of delay testing for multi-clock circuits; (2) instruction-based testing methods for microprocessor; (3) functional test and built-in self-test methods for globally-asynchronous, locally-synchronous circuits; (4) distributed compression/decompression structure based on random access scan design; (5) test scheduling methods based on test access bus. Experiments will be conducted on digital VLSI circuits, especially for multi-core microprocessor, with billions of transistors under 90-to-60 nano-metre processes. Original methods and key techniques will be proposed, as well as prototype software tools. Effective pre-verified methods and key techniques will be provided for testing digital VLSI circuits, especially for multi-core microprocessor, with billions of transistors under 60-to-45 nano-metre processes.
     

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