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    Emerging NVM Enabled Computing Architecture – From Evolution to Revolution
    Update time: 2012-07-25
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    Time: 10:00-12:00am,July 27th, 2012 (Friday)

    Place: 446 Room, ICT, CAS


    The continuously increased technical challenges for the scaling of mainstream memory technologies inspired the tremendous investment on the next-generation nonvolatile memory (NVM) technologies. Many candidates, i.e., phase change memory, spintronic memory, and resistive memory, have been identified and studied. Various new applications are innovated based on these new memory technologies due to their many attractive characteristics such as non-volatility, high cell density, nanosecond access time and low operating voltage etc. In this presentation, we will start with the application examples of the emerging NVM in the different locations of the memory hierarchy of modern computing architecture, where emerging NVM demonstrates unparalleled advantages on capacity, power, system performance and robustness. After that, we will introduce a new neuromorphic computing diagram based on memristor crossbar array. Different from the popular synapse-based designs, this scheme offers a highly condensed implementation of neuron network model without the general worries such as sneak paths etc. By leveraging the computing and storing capability of memristor devices and the innovated hardware platform, we are trying to achieve a power efficiency of 1000 GFLOPS/w or higher.


    Yiran Chen received B.S. and M.S. (both with honors) in EE from Tsinghua University, China and Ph.D. in ECE from Purdue University, W. Lafayette, IN. Before he joined University of Pittsburgh in 2010, he worked with Synopsys and Seagate for 5 years. Dr. Chen’s research interests include VLSI design, nano-electronic devices and embedded systems. He has published more than 100 technical publications, has 63 granted US patents and other 21 pending applications. He coauthored one book - “Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing”, as well as other several book chapters. He is the associate editor of TCAD and the editor of JETC. He served as technical and organizational committees of many conferences, including DAC, ICCAD, DATE, ASP-DAC, ISLPED, FPT, ISCAS, CODES+ISSS, etc. During 2007-2010, he served as the patent review board member of Seagate memory product group. As a key developer of PrimeTimeVX, Dr. Chen received "The hot 100 products of 2006" from EDN, “EDN 100 Hot Products Distinction” from Synopsys and the finalist of "Prestigious 2007 DesignVision Awards" from IEC. His works also received two best paper awards from ISQED 2008 and ISLPED 2010, respectively, and were nominated as the best paper candidates in ISQED, DATE, and ASPDAC etc. for multiple times. His Ph.D. student is the recipient of A. Richard Newton Scholarship. He is the inventor of “Spintronic Memristor”.


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