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    The hardware management of concurrency in the Microgrid and the fungibility of processing resources
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    Update time: 2012-07-03
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    Time: 10:00-11:30 a.m., July. 4, 2012 (Wednesday)

    Place:Room 1201, ICT. CAS

    Speaker: Prof. Chris Jesshope

    Abstract

    This presentation will give an introduction to the work undertaken in project Apple-CORE on the development of a multi-threaded, many-core processor and system software. The aim of this project has been to develop a general purpose many core system that relies on space sharing rather than time sharing to manage concurrent activities. To achieve this generality, one of the key aims has been to capture binary code in a concurrent form and to execute this code unchanged on a dynamically selected set of resources that may be a single thread slot or many cores and thousands of threads. This approach uses an automatically managed sequential schedule over the concurrency expressed in the binary code, using both hardware and software techniques. To implement this, the processing resources must be dynamically partitionable (the fungibility) and the management of concurrency must be implemented in the ISA of the processor. The talk will give an overview of the project and give an introduction to the key aspects of the architecture and how concurrency is managed. The project has produced a cycle-accurate emulation of the many core chip, an FPGA prototype of a single core with transparent hardware acceleration of some functions, compilers and system software. The compilers include a concurrent C-like system language as well as a parallelising C compiler and a high level data-parallel functional language.

    Bio

    Chris Jesshope has a broad educational background including Mathematics, Computer Science and Electronics. Since 1976 he has been actively involved all aspects of concurrency in computer systems, first as an applications' programmer using the first parallel supercomputers available at that time, such as the Cray , ICL DAP and Illiac V. Later as a computer architect working on reconfigurable SIMD computers at the VLSI level and reconfigurable MIMD computers based on transputers at the system level. For the last decade he has been working on concurrency at the instruction level in conventional microprocessors. The approach to concurrency developed during this time has the potential to support the scaling of concurrency in microprocessors to the end of CMOS and across a wide range of applications. Chris Jesshope was until recently the leader of the Computer Systems Architecture Group at University of Amsterdam but is now an emeritus Professor (retired) at the University of Amsterdam as well as a Consultant and professorial-level researcher at the University of Hertfordshire. His interests are in microarchitecture and concurrent systems with an emphasis on hardware managed concurrency in future systems. He has published in excess of 150 refereed conference and journal papers in the above fields as well as 15 books and book chapters, including the much cited book Parallel Computers, written jointly with professor Hockney.
     

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