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    Applications of Multi-threaded processors
    Update time: 2012-07-03
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    Time: 10:00-11:30 a.m., July. 6, 2012 (Friday)

    Place:Room 1201, ICT. CAS

    Speaker: Prof.Chris Jesshope


    The objective of this talk is give a more in depth view of the issues we have had to solve in the development of the Apple-CORE project and to present some preliminary results from the application of the many core chip. It will also describe some new directions we are tackling in a joint project with the European Space Agency (ESA) to investigate the benefit of multi-threaded processors in space applications.
    It will consider generic applications as well as two specific areas which are critical for space missions: (a) real-time tasks and (b) reliability. We believe that multi-threading can provide tighter bounds for WCET for real-time tasks and more efficient support redundant execution due to the flexibility enabled by multi-threaded applications. The general advantages of this technology with respect to traditional single threaded processors are :
    · tolerating long latency operations without stalling the pipeline, e.g. off-chip memory operations or off-loading computation to functions implemented in hardware;
    · faster program execution due to fewer pipeline stalls; and
    · more processing power per watt of power expended due to higher pipeline efficiencies and conservative instruction execution.
    To these generic advantages we will will show there are two further advantages that tackle significant constraints in space applications. These arise from the flexibility that multi-threading can provide in the support of reliability with respect to soft errors and secondly in timing predictability with respect to hard real-time processes. Flexibility is required to distinguish between different classes of application that may have differing requirements, e.g. differing payload applications and control processes.


    Chris Jesshope has a broad educational background including Mathematics, Computer Science and Electronics. Since 1976 he has been actively involved all aspects of concurrency in computer systems, first as an applications' programmer using the first parallel supercomputers available at that time, such as the Cray , ICL DAP and Illiac V. Later as a computer architect working on reconfigurable SIMD computers at the VLSI level and reconfigurable MIMD computers based on transputers at the system level. For the last decade he has been working on concurrency at the instruction level in conventional microprocessors. The approach to concurrency developed during this time has the potential to support the scaling of concurrency in microprocessors to the end of CMOS and across a wide range of applications. Chris Jesshope was until recently the leader of the Computer Systems Architecture Group at University of Amsterdam but is now an emeritus Professor (retired) at the University of Amsterdam as well as a Consultant and professorial-level researcher at the University of Hertfordshire. His interests are in microarchitecture and concurrent systems with an emphasis on hardware managed concurrency in future systems. He has published in excess of 150 refereed conference and journal papers in the above fields as well as 15 books and book chapters, including the much cited book Parallel Computers, written jointly with professor Hockney.

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