Home Sitemap Contact 中文 CAS
 
Navigation
  • HOME
  • About Us
  • Research
  • People
  • International Cooperation
  • News
  • Education & Training
  • Join Us
  • Publications
  • Papers
  • Resources
  • Links
  • Location:Home>News>Upcoming Events
    Quality of Test – Fault Models and Test Methods
    Author:
    ArticleSource:
    Update time: 2012-06-14
    Close
    Text Size: A A A
    Print

    Time: : 10:00-12:00am,June28th,2012(Thursday)

    Place:446 Room, ICT, CAS

    Speaker:Janusz Rajski

    Abstract:

    The actual quality of manufacturing test is a result of the required product quality expected by the market that can be achieved in a given semiconductor technology with the currently available test methods at acceptable costs. As the quality requirements and semiconductor technology change, the test methods have to change accordingly. This paper discusses how recent as well as the soon expected to appear characteristics of semiconductors will change defect profiles and what changes are expected to happen in test methodology.

    The devices manufactured in the 30, 20 and 10 nm technologies will potentially be very large by today’s standards, they will also have new characteristics implied by things like process variability. The semiconductor industry has adopted cumulatively more and more sophisticated fault models that use timing as well as layout information. What other fault models will be required to provide a robust measure of quality of test? The presentation will review some of the most promising extensions in that area, including new emerging fault models and adaptive test techniques.

    Structural DFT was introduced to provide automation in test pattern generation and fault simulation. Test compression was invented, on top of scan, to reduce the cost of manufacturing test. What other technologies will be needed to address the issue of growing design sizes, increased process variability, and new defect mechanisms? What is the impact of 3D IC technology on test methods. The presentation will examine hybrid techniques that use test compression and logic BIST to achieve manufacturing test objectives as well as system reliability.

    bio:

    Janusz Rajski is a chief scientist and the director of engineering for the Silicon Test Solutions products group at Mentor Graphics. He has published more than 200 research papers in these areas and is co-inventor of 68 US patents. He is also the principal inventor of Embedded Deterministic Test (EDT™) technology used in the first commercial test compression product TestKompressÒ. He was co-recipient of the 1993 Best Paper Award for the paper on logic synthesis published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, co-recipient of the 1995 and 1998 Best Paper Awards at the IEEE VLSI Test Symposium, co-recipient of the 1999 and 2003 Honorable Mention Awards at the  IEEE  International Test Conference, co-recipient of the 2010 Best Paper Award at the IEEE European Test Symposium, co-recipient of the 2008 Best Paper Award at the Asian Test Symposium, and 2009 Best Paper Award at the VLSI Design, as well as co-recipient of the 2006 IEEE Circuits and Systems Society Donald O. Pederson Outstanding Paper Award recognizing the paper on embedded deterministic test published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. He served as Program Chair of the IEEE International Test Conference. In 2009 he received the Stephen Swerling Innovation Award from Mentor Graphics “for his breakthrough innovation, TestKompress, and his many contributions to revitalizing Mentor's DFT business to its current position as #1 test business in EDA”. In 2011 Janusz was elevated to the grade of IEEE Fellow for ”contributions to VLSI circuit testing and test compression”.

     

    Address :No.6 Kexueyuan South Road Zhongguancun,Haidian District Beijing,China
    Postcode :100190 Tel : (8610)62601166 Email : office@ict.ac.cn