Time： 15:00-16:00 pm , May 10, 2012 (Thursday)
Place：Room 1201, ICT. CAS
Speaker: Prof. Israel Koren
Asymmetric multicore processors (AMPs) have been shown to outperform symmetric ones in terms of performance and performance/watt.The improved performance and power efficiency are achieved when the program threads are matched to their most suitable cores.Since programs change their computational needs during their execution, the best thread to core assignment will likely change with time. We have therefore, developed an online program phase classification scheme that allows swapping of threads when the current needs of the threads justify a change in the assignment.
The architectural differences among the cores in an AMP can never match the diversity that exists among different programs and even between different phases of the same program. Consider, for example, a program (or a program phase) that has a high instruction level parallelism (ILP) and will exhibit high power efficiency if executed on a powerful core. We can not however, include in the designed AMP, such powerful cores since they will remain underutilized most of the time, and they are not power efficient when the programs do not exhibit high degree of ILP. Thus, we must expect to see program phases where the designed cores will be unable to support the ILP that the program can exhibit. We therefore, propose in this talk a dynamic morphing scheme. This scheme will allow a core to gain control of a functional unit that is ordinarily under control of a neighboring core, during periods of dense computation with high ILP. This way, we dynamically adjust the hardware resources to the current needs of the application.
Our results show that combining online phase classification and dynamic core morphing can significantly improve the performance/watt of most multi-threaded workloads.
Israel Koren is a Professor of Electrical and Computer Engineering at the University of Massachusetts, Amherst and a fellow of the IEEE. He has been a consultant to companies like IBM, Analog Devices, Intel, AMD and National Semiconductors. His research interests include Fault-Tolerant systems, secure cryptographic devices, VLSI yield and reliability, Computer architecture and computer arithmetic. He publishes extensively and has over 250 publications in refereed journals and conferences. He is the author of the textbook "Computer Arithmetic Algorithms," 2nd Edition, A.K. Peters, Ltd., 2002, a co-author of the textbook "Fault Tolerant Systems,“ Morgan-Kaufman, 2007.