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    Non-Volatile Memory Architecture for the Performance, Energy Consumption, and Reliability Improvement
    Update time: 2011-09-21
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    Speaker: Guangyu Sun Center for Energy Efficient Computing and Applications Peking University
    Time: 14:30 ~ 16:00 PM, Sept. 26, 2011
    Place: Room 446, Institute of Computing Technology
    Recently, various non-volatile memory (NVM) technologies have been proposed as candidates for the design of the future memory hierarchy because of their advantages, such as high density, zero standby power, fast access speed, non-volatility, etc. With these emerging NVMs, the memory hierarchy design needs to be rethought to achieve high performance, low power consumption, and high reliability. Since these emerging memory technologies have different characters, the following three questions should be answered to achieve the design goals: (1) how to choose the proper memory technologies in the design of different levels of a memory hierarchy? (2) how to improve the architecture of a traditional memory hierarchy to facilitate the adoption of these emerging memories? (3) how to leverage the advantages of different memory technologies? In this talk, we intend to answer these questions by exploring the memory hierarchy design in two different levels. We will show that both performance and power consumption can be improved after we apply modifications to the memory architectures (HPCA09 and ICCD11). At the same time, we find it is attractive to leverage advantages from different memory technologies by using the hybrid memory design (HPCA10).
    Dr. Guangyu Sun is an assistant professor in the Center for Energy Efficient Computing and Applications (CECA) at the Peking University. He received his BS and MS degrees from the Tsinghua University and received his Ph.D. degree in Computer Engineering from the Pennsylvania State University. Dr. Guangyu Sun’s research interests are in the field of computer architecture with an emphasis on memory systems and three dimension (3D) architectures. He is also interested in heterogeneous processor architecture, 3D and process-variation aware VLSI design, and CAD tools development. Recently, he has extensively researched on the design exploration of different emerging memory technologies, such as STTRAM and PCM, in architecture and circuit levels.

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