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    Design for Resilience in Nanometer CMOS and 3D-IC
    Update time: 2010-06-29
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    Time:  15:00  June 30th,2010
    Place:  Room 440, 4th Floor, ICT, CAS
    Speaker:  David Z. Pan,Associate Professor of University of Texas at Austin

    He will first give a brief overview of the key researches conducted by his group. Then He will focus on the design for manufacturability and reliability/robustness issues in nanometer CMOS and 3D-IC. For 22nm node and below, lithography is facing tremendous challenges and double patterning lithography (DPL) is the forerunner for 22nm/16nm. He will present a novel multi-objective layout decomposition framework that can simultaneously minimize stitches, self-compensate overlay variations, and balance the patterning density. The DPL effect shall also be considered during physical design, in particular routing to achieve better solution quality and layout compliance. For nanometer CMOS, aging effect due to NBTI is a serious problem. He will show both design and CAD techniques to compensate the aging effect due to NBTI. For 3D-ICs, through silicon vias (TSV) cause thermal-mechanical stress effects which affect timing and reliability. They develop the first-order compact model for stress-induced mobility and timing variations, which can be used for TSV and cell layout optimizations. 

    David Z. Pan is currently an Associate Professor (with tenure) at the Department of Electrical and Computer Engineering, University of Texas at Austin, where he directs the UT Design Automation (UTDA) Lab. He received his Ph.D. in computer science (with honor) from UCLA in 2000. He was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. His research is mainly focused on design for manufacturing/reliability, nanometer physical design, intersection of physical and system-level co-design, and design/CAD for emerging technologies. He holds 8 U.S. patents and has published over 120 technical papers in premier journals and international conferences.

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