CV of Zhimin Tang
Basic Information
· NAME: Tang, Zhimin
· E-MAIL: tang@ict.ac.cn
Education
· Ph. D in Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences (ICT-CAS), March 1990
· BS in Computer Science, Department of Computer Science, Nanjing University, July 1985
Interested Research Areas
· Advanced Computer Architecture
· Parallel and Distributed Computing
· Microprocessor and SoC (System-on-Chip) Design
Professional Experiences
· 1990, Assistant Professor, Institute of Computing Technology (ICT for short)
· 1990-1991, Development of Parallel C Language, Compiler and Operating System for BJ-01, An Experimental Parallel Computer Based on Motorola 68020 CPUs
· 1992, Associate Professor, ICT
· 1992-1994, Development of BJ-1 Parallel Computer based on Intel i860XP CPUs, and Design and Implementation of High Speed Wave Pipelining Arithmetic Units based on 1.5 micron CMOS Gate Array
· 1995, Full Professor, ICT
· 1995-1997, Research and Development of Distributed Shared Memory Systems, and Design of Crossbar-based Scalable Interconnection Networks
· 1996, Associate Director, Research Center for High Performance Computers, ICT
· 1998, Associate Director, Department of Computer System Architectures, ICT
· 1998-2000, Member of the Executive Group of NHPCE (National High Performance Computing Environment, a major project of National High Technology Program), in charge of Grid Software and Network Infrastructure (part-time)
· 1999, Director, Department of Computer System Architectures, ICT
· 2001-2004, Executive member of Expert Group of Computer Hardware and Software Technology, National High Technology (863) Program, in charge of Next Generation Internet and Computer Architecture (part-time)
· 2001-2005, Chief Scientist and Project Manager of Goodson (or Dragon Chip, currently named Loongson) CPU Project, a major project supported by CAS to develop 32-bit Goodson-1 and 64-bit Goodson-2 microprocessors
· 2002-2004, Assistant Director of ICT, in charge the management of R&D projects of the Institute, and all chip related business
· Aug-Dec 2004, General Manager, BLX IC Design Company, Beijing (part-time)
· 2005-2006, Assistant Chief Scientist of the “Novel Principles, Architectures, and Methods of Future Micro-Processing Chips” Project, supported by National Basic Research (or 973) Program of China
· Feb-Apr 2006, General Manager, Suzhou CAS IC Design Center (A Non-Profit Organization founded by ICT and Suzhou Municipal Government), Suzhou (part-time)
· May 2006 - Oct 2011, President, ApaceWave Technologies, Ltd., a silicon valley based startup developing terminal SoC chips and solutions compliant with mobile WiMAX (IEEE 802.16e) standards
· Nov 2011 - present, Professor, State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Journal Editorship
· Editor, Science in China: Information Sciences (published by Science Press and Springer in both Chinese and English monthly)
· Editor, Chinese Journal of Computers (published by Science Press in Chinese monthly)
· Executive Editor-in-Chief, Communications of the CCF (published by Chinese Computer Federation in Chinese monthly)
Professional Services
· Member, Eighth National committee of China Association for Science & Technology
· Director, Working Committee of Computer Terminology, Chinese Computer Federation
· Executive Member, Technical Committee of Information Storage, Chinese Computer Federation
· Member, Technical Committee of Computer Architecture, Chinese Computer Federation
Awards
· Awards for Best Journal Papers, China Association for Science & Technology, 2007
· Prize for Chinese Young Scientific and Technological Professionals, awarded by Chinese government in 2004
· Outstanding Science and Technology Achievement Prize of the Chinese Academy of Sciences, 2003
· Prize for Young Scientists, Chinese Academy of Sciences, 1998
· Prize for Progress in Science and Technology, Chinese Academy of Sciences, 1995
List of Selected Publications
1. “Optimal Granularity of Grid Iteration Problems”, in Proceedings of 1990 International Conference on Parallel Processing，Vol. I, 111-118, August 1990 (with Guojie Li)
2. “On the Reduction of Connections in Hopfield Associative Memories”, in Proceedings of 1991 China International Conference on Circuits and Systems，282-285, July 1991 (with Guojie Li)
3. “Pipelined Global Data Communication on Hypertoruses”, Journal of Computer Science and Technology，Vol.7, No.3, 247-256, May 1992
4. “System Software of BJ-01 Parallel Computer”, Chinese Journal of Computers, Vol.16, No.12, 903-910, December 1993 (with Dahai Huang, in Chinese).
5. “Maximum Time Difference Pipelined Arithmetic Units Based on CMOS Gate Array”, Journal of Computer Science and Technology, Vol.10, No.2, 97-103, March 1995 (with Peisu Xia)
6. “High Performance Computers and Computational Science”, Chinese Science Bulletin，Vol.41, Supplement，28-35，May 1996 (in Chinese)
7. “A New Method for Cache Optimization: Partial Cache Locality”, Chinese Journal of Computers，Vol. 27, No. 1, pp.1-7, January 1997 (with Ming Li, in Chinese)
8. “Consummating Virtuality to Support More Polymorphism in C++”, ACM SIGPLAN Notices, 32(6), 61-68, June 1997 (with Wenke Chen)
9. “Essential Issues in Distributed Memory Parallel Systems”, Computer Engineering and Science，Vol.20, Supplement，19-23，October 1998 (in Chinese)
10. “A Lock-Based Cache Coherence Protocol for Scope Consistency”, Journal of Computer Science and Technology, Vol. 13, No. 2, 97-109, March 1998 (with Weiwu Hu)
11. “Memory Complexity in High Performance Computing”, in Proceedings of HPCAsia'98, 142-151, Singapore, August 1998 (with Yunquan Zhang)
12. “Reducing System Overheads in Home-Based Software DSMs”, in Proceedings of the 1999 International Parallel Processing Symposium，167-172, San Juan, Poto Rigo, April 1999 (with Weiwu Hu)
13. “JIAJIA: A Software DSM System Based on a New Cache Coherence Protocol”, in Proceedings of the 1999 International Conference on High Performance Computing and Networking Europe，LNCS 1593, 463-472, Amsterdam, April 1999 (with Weiwu Hu)
14. “Shared Memory verses Message Passing on Dawning 1000A”，Chinese Journal of Computers, Vol.23, No.2, 134-140, February 2000 (in Chinese)
15. “Using Building Blocks Construct Deep Submicron Wave Pipelined system”, in Proceedings of the First Portugal-China Workshop on Solid-State Circuits, 101-102, Shanghai, China, Oct. 2000 (with Lan Chen)
16. “Study of a Novel Interconnection Network”, Chinese Journal of Computers, 23(8), August 2000, 785-792 (with Zhiyu Zhou, in Chinese)
17. “Load Balancing in Home-Based Software DSMs”, International Journal of Foundations of Computer Science, 12(3), 307-324, 2001 (with Weisong Shi)
18. “Optimizing Home-based Software DSM Protocols”, Cluster Computing, 4(3), 2001 (with Weiwu Hu)
19. “Reducing Contention in Multiple Multicasts”, in Proceedings of the 20th IEEE International Performance, Computing, and Communications Conference (IPCCC'2001), Phoenix, Arizona, April 4-6, 2001 (with Zhiyu Zhou)
20. “Design issues of deep submicron wave pipelining technology”, in Proceedings of the 4th IEEE International Conference on ASIC, Oct.2001, Shanghai (with Lan Chen)
21. “Compiler Optimization for Low Power and Multithreading Architectures”, Journal of Software, 13(6), 2002 (with Rongcai Zhao, in Chinese)
22. “Compiler Directed Low Power Design for Multithreading Architectures”, Computer Research and Development, 39(12), 2002 (with Rongcai Zhao, in Chinese)
23. “Design Technology of System-on-Chip (SOC)”, Computer Research and Development, 39(1):9-16, Jan. 2002 (with Lan Chen, in Chinese)
24. “Microarchitecture Design of Goodson-1 Processor”, Chinese Journal of Computers, 2003, 26(4):385-394 (with Weiwu Hu, in Chinese)
25. “Comparing the Performance of JIAJIA and MPI on a PC Cluster”, Journal of Software, 14(7):1187-1194, 2003 (with Mingchang Hu, in Chinese)
26. “Low Power Compiler Optimization for Software Pipelining”, Journal of Software, 14(8), 2003 (with Rongcai Zhao, in Chinese).
27. “Design and Implementation of a Cluster-based OpenMP System”, Chinese Journal of Computers, 27(7): 904-912, July 2004 (with Shaogang Wu, in Chinese).
28. “Parallel program performance evaluation and their behavior analysis on an OpenMP cluster”, in Proceedings of the 4th IEEE/ACM International Symposium on Cluster Computing and the Grid, 508-514, April 2004 (with Fei Cai)
29. “Trends of Chip Multiprocessors”, Communications of the CCF, 1(1):23-30, 2005 (in Chinese)
30. “TLB Design Methods of Embedded Processors”, Chinese Journal of Computers, 29(01):73-80, 2006 (with Dongrui Fan, in Chinese)
31. “SimOS-Goodson: a Multi-Core Full System Simulator Based-on Goodson CPU”, Journal of Software, 18(04):1047-1055, 2007 (with Xiang Gao, in Chinese)
32. “Chip Multithreaded Consistency Model”, Journal of Computer Science and Technology, 23(02):298-303, 2008 (with Zusong Li)
33. “Simultaneous Multi-Threading Design of Goodson-2 Processor”, Chinese Journal of Computers, 32(11):2265-2274, November 2009 (with Zusong Li, in Chinese)
34. “Efficient Recoding of Conflict Memory Accesses to Support Deterministic Replay of Multi-Core Parallel Programs”, Computer Research and Development, 49(01):64-76, January 2012 (with Lei Liu, in Chinese)
35. “Computer Architecture Combining Computing and Communication”, Journal of Integration Technology, 1(1):88-91, May 2012 (in Chinese)
