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    Lixin Zhang
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    Update time: 2013-04-01
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    CURRICULUM VITAE of
    Lixin Zhang
    RESEARCH INTERESTS
    Computer architecture, data center computing systems, advanced cache/memory systems, architectural simulators, distributed/parallel computing, performance evaluation, and workload characterization.
    EDUCATION
    Ph.D. (Computer Science), University of Utah, 12/2001
    Dissertation: Efficient Remapping Mechanisms for An Adaptable Memory System
    M.S. (Computer Science), Fudan University, 07/1995
    B.S. (Computer Science), Fudan University, 07/1993
    WORK EXPERIENCE
    Quick Index:
    08.2010  Present: Professor, Institute of Computing Technology, Chinese Academy of Sciences
    09.2003  08.2010: Research Staff Member & Lead Research Advisor, IBM Research
    01.2002  08.2003: Postdoctoral Research Associate, University of Utah
    07.1999  12.2001: Research Staff Member, University of Utah.
    01.1996  06.1999: Research Assistant, University of Utah
    09.1995  12.1995: Teaching Assistant, University of Utah
    07.1994  07.1995: Software engineer, Kingstar Computer Co.
    09.1991  07.1994: Research Assistant, Fudan University
    1. 08.2010  Present: Professor, Vice General Engineer, Institute of Computing Technology, CAS
    Director, Advanced Computer Systems Laboratory
    I lead the Advanced Computer Systems Laboratory. My team is currently exploring new ways to build the next-generation data center servers. We are looking for opportunities across the entire hardware and software stack, including ISAs, chip/memory/storage/network architectures, system software, run-time environment, data center management systems, etc.
    2. 09.2003  08.2010: Research Staff Member, IBM Austin Research Lab.
    PERCS (Productive, Easy to use, Reliable Computer Systems). The goal of PERCS is to deliver a multi-petaflop high performance computer. As a key member of the architecture/performance team, I led or co-led the design and evaluation of various CMP cache memory hierarchies, including advanced cache coherence protocols, intra-chip cache communication topology, near memory processing, high performance memory hubs, memory in processor, and advanced data prefetching mechanisms. I also led the development of the PERCS simulator and developed its cycle accurate processor and nest models. I am a lead performance architect of the 10 Petaflops machine Blue Waters, initially scheduled to come out in 2011, but later cancelled by IBM.
    Power7, I led the development of a cycle-accurate model in a full-system simulation environment for the Power7 microprocessor. The model was about two orders of magnitude faster than IBMˇs existing simulator used by the product team at that time with comparable accuracy. I, working with the Chief Architects and other members in the research team and the development team, used this model to (i) to refine designs of various units in Power7, (ii) to push research ideas into the Power7, and (iii) to perform competitive analysis.
    TRIPS (Tera-op, Reliable, Intelligently adaptive Processing System). I studied various NUCA (non-uniform cache architecture) organizations for flexible CMP cache sharing mechanisms.
    STI (a.k.a., Cell). I developed cycle-accurate simulator models for the on-chip interconnect bus, cache coherence engine, and memory system of the Cell architecture. I also provided consulting services to its simulator development team.
    ACAS (IBM Austin Center for Advanced Studies). I was the Lead Research Advisor in the system & software area. I was responsible for reviewing/ranking proposals for IBM faculty awards and PhD fellowship awards and helping organize semi-annual CAS conferences.
    3. 01.2002  08.2003: Postdoctoral Research Associate, University of Utah. I was a university partner of SGIˇs Ultraviolet project, whose goal was to design, evaluate, and produce peta-scale systems.
    I led the design of Active Memory Systems, which exploited the potential and feasibility of incorporating processing power into the memory controllers.
    I led the development of the simulator infrastructure used by the entire Ultraviolet team, which included researchers at SGI, MIT, George Washington University, and University of Utah.
    I led the design of scalable coherence mechanisms and scalable synchronization mechanisms for large-scale CC NUMA systems.
    I acted as the technical leader for a team of three graduate students and one undergraduate student.
    4. 07.1999  12.2001: Research Associate, University of Utah As a full-time staff member of the Impulse Adaptable Memory Systems project, I played a leading role in the design/evaluation phase and a key role at the development phase. Overall, I had been a major contributor to
    the architecture-level design,
    simulator development,
    kernel extension,
    application analyses and performance evaluation, and
    chip-level functional verification of the ASIC design.
    5. 07.1996  07.1999: Research Assistant, University of Utah
    This was for my dissertation work. The key idea was to use an intelligent memory system to significantly increase the performance of the processor caches and the system bus by allowing applications to control how data should be present to the caches during runtime. For instance, multiple sparsely store data items in the memory may be merged a dense line in a cache.
    04.1996  12.1996: Research Assistant for project Avalanche Scalable Parallel Processor, University of Utah Avalanche entailed the design and construction of a usable and scalable parallel computing platform that was not exorbitantly expensive, yet still capable of achieving high performance. My work was to design, simulate, and evaluate an assist cache and a hardware-directed cache prefetching mechanism.
    01.1996  04.1996: Research Assistant for project Module Manipulation, University of Utah Worked as a programmer for this project, which added modularity to existing languages by providing a suite of operators that accept modules as arguments and produce modules as results.
    09.1995  12.1995: Teaching Assistant for class Digital System Design, University of Utah Grader and lab tutor for this undergraduate-level class about the fundamental concepts of digital system theory and design.
    07.1994  07.1995: Software engineer, Kingstar Computer Co., P.R.China Project manager and main developer of a four-member team to build a LAN-based system that traces
    manufacturing information in real time and generates instant feedbacks.
    09.1991  07.1994: Research Assistant for project ¨Remote Procedure Call〃, Fudan University Primary programmer of a project to implement the remote procedure call paradigm in a special environment.
    09.1991  07.1993: Research Assistant for project ¨OSI High Level Protocol Implementation Based On TCP/UDP/IP〃, Fudan University Principal designer and programmer of an effort to implement the transport layer of the ISO/OSI model based on the TCP/UDP/IP implementation.
    PUBLICATIONS
    Journal Papers
    PERCS System Architecture.
    E. N. Elnozahy, Evan Speight, Jian Li, Ramakrishnan Rajamony, Lixin Zhang and L. Baba Arimilli.
    Encyclopedia of Parallel Computing, Sept. 2011
    Design Exploration of Hybrid cache architecture with disparate memory technologies.
    Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ram Rajamony and Yuan Xie.
    ACM Transaction on Architecture and Code Optimization (TACO), Dec 2010
    A NUCA Substrate for Flexible CMP Cache Sharing
    Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger and Stephen W. Keckler. Journal of IEEE Transactions on Parallel And Distributed Systems, Vol. 18, No. 8, pp 1028-1040, Aug 2007.
    Efficient Address Remapping in Distributed Shared-Memory Systems Lixin Zhang, Mike Parker and John B Carter. Journal of ACM Transactions on Architecture and Code Optimization, Vol. 3, Issue 2, pp 209-229, June 2006.
    Application of Full-System Simulation in Exploratory System Design and Development J.L. Peterson, P.J. Bohrer, E.N. Elnozahy, A. Gheith, R.H. Jewell, M.D. Kistler, T.R. Maeurer, S.A. Malone, D.B. Murrell, N. Needel, K. Rajamani, M.A. Rinaldi, R.O. Simpson, K. Sudeep, Lixin Zhang. IBM Journal of Research and Development, Vol. 50, No. 2/3,, pp. 321-333, 2006.
    Fast Synchronization on Shared-Memory Multiprocessors: An Architectural Approach Zhen Fang, Lixin Zhang, Liqun Cheng, John B Carter and Mike Parker. Journal of Parallel and Distributed Computing, 2005.
    Scalable Barriers for Large-scale Shared Memory Multiprocessors Zhen Fang, Lixin Zhang, John B Carter and Mike Parker. International Journal of High Performance Computing and Networking, Vol. 6 2004.
    Mambo -- A Full System Simulator for the PowerPC Architecture P. Bohrer, M. Elnozahy, A. Gheith, C. Lefurgy, T. Nakra, J. Peterson. R. Rajamony, R. Rockhold, H. Shafi, R. Simpson, E. Speight, K. Sudeep, E. Van Hensbergen, and L. Zhang. ACM SIGMETRICS Performance Evaluation Review, Volume 31, Number 4, March 2004
    The Impulse Memory Controller Lixin Zhang, Zhen Fang, Mike Parker, Binu Mathew, Lambert Schaelicke, John B Carter, Wilson C Hsieh, and Sally A McKee. Transactions on Computers, Vol 50, No. 11, pp 1117-1132, November 2001.
    Impulse: Memory System Support for Scientific Applications John B Carter, Wilson C Hsieh, Leigh Stoller, Mark Swanson, Lixin Zhang, and Sally A McKee. Journal of Scientific Programming, Vol 7, No 3-4, pp. 195-209, 1999.
    Transition from TCP/IP to OSI protocol Lixin Zhang, Zhaodong Cui, and Chuanshan Gao. Journal of Computer Applications and Software (ISSN 1000-386X), Vol. 12, No. 2, pp. 1-7, 1995.
    RPC and Its implementation in UNIX Environment Chuanshan Gao, Bo Wu, Lixin Zhang, and Xiangyang Chen. Computer Engineering Journal (ISSN 1000-3428), Vol.19, No.5, pp. 37-42, 1993.
    Refereed Conference and Workshop Papers
    Characterization of Real Workloads of Web Search Engines
    Huafeng Xi, Jianfeng Zhan, Zhen Jia, Xuehai Hong, Lixin Zhang and Ninhui Sun In the Proceedings of IEEE International Symposium on Workload Characterization, Nov., 2011
    Application-driven Energy-efficient Architecture Explorations for Big Data
    Xiaoyan Gu, Rui Hou, Ke Zhang, Lixin Zhang and Weiping Wang In the Proceedings of The First Workshop on Architectures and Systems for Big Data, Oct., 2011
    Adapt or Become Extinct!
    G. Goumas, S. A. McKee, M. Sjalander, T. R. Gross, S. Karlsson, and L. Zhang In the Proceedings of IEEE Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era, Jun. 2011
    Power Shifting in Thrifty Interconnection Network
    Jian Li, Lixin Zhang, Wei Huang, Charles Lefurgy, Wolfgang Denzel, Richard Treumann, Kun Wang
    In the Proceedings of International Symposium on High Performance Computer Architecture, Feb., 2010.
    Efficient Data Streaming with On-chip Accelerators: Opportunities and Challenges
    Rui Hou, Lixin Zhang, Michael C Huang; Kun Wang, Hubertus Franke, Yi Ge, Xiao Tao Chang
    In the Proceedings of International Symposium on High Performance Computer Architecture, Feb., 2010.
    Thrifty Interconnection Networks for HPC systems
    Jian Li, Lixin Zhang, Charles Lefurgy
    Abstract in proceedings of International Conference on Supercomputing, New York, June, 2009.
    Power and Performance of Read-Write Aware Hybrid Caches
    Xiaoxia Wu, Jian Li, Evan Speight, Lixin Zhang and Yuan Xie,
    In Design, Automation & Test in Europe (DATE) 2009, Nice, France, April 20-24, 2009
    Power and performance evaluation for 3D hybrid cache with non-volatile memory
    Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight and Yuan Xie,
    In HPCA 3D Workshop, Raleigh, North Carolina- February 15, 2009
    Light-weight predication support in OOO superscalar processors
    Mark Stephenson,, Lixin Zhang, and Ram Rangan
    In the Proceedings of International Symposium on High Performance Computer Architecture, Feb. HPCAˇ2009
    Active Memory Operations Zhen Fang, Lixin Zhang, John Carter, Ali Ibrahim and Mike Parker. In the Proceedings of the 21st International Conference on Supercomputing, June 2007
    A NUCA Substrate for Flexible CMP Cache Sharing Jaehyuk Huh, Changkyu Kim , Hazim Shafi, Lixin Zhang, Doug Burger, and Stephen W. Keckler. In the Proceedings of the 19th ACM International Conference on Supercomputing, June 2005
    Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors Evan Speight, Hazim Shafi, Lixin Zhang, and Ram Rajamony
    In the Proceedings of the 32nd Annual International Symposium on Computer Architecture, Madison, Wisconsin, June 2005.
    Highly Efficient Synchronization Based on Active Memory Operations Lixin Zhang, Zhen Fang and John B Carter. In the Proceedings of the International Parallel and Distributed Processing Symposium, April 2004
    Super-Fast Active Memory Operations-Based Synchronization Lixin Zhang, Zhen Fang, John B. Carter, and Mike Parker The 2nd Workshop on Hardware/Software Support for High Performance Scientific and Engineering Computing, September 2003.
    Reevaluating Online Superpage Promotion with Hardware Support Zhen Fang, Lixin Zhang, John B Carter, Sally A McKee, Wilson C Hsieh. In the Proceedings of the Seventh International Symposium on High Performance Computer Architecture , pp. 63-72, January 2001
    Memory System Support for Dynamic Cacheline Assembly Lixin Zhang, Venkata K Pingali, Bharat Chandramouli, and John B Carter. In the 2nd Workshop on Intelligent Memory Systems, August, 2000.
    Pointer-Based Prefetching within the Impulse Adaptable Memory Controller: Initial Results Lixin Zhang, Sally A McKee, Wilson C Hsieh, and John B. Carter. In the ISCA-2000 Workshop on Solving the Memory Wall Problem, June 2000.
    Online Superpage Promotion Revisited Zhen Fang, Lixin Zhang, John B Carter, Sally A McKee, and Wilson C Hsieh. In the Proceedings of SIGMETRICS 2000 International Conference on Measurement and Modeling of Computer Systems, June 2000.
    Memory System Support for Image Processing Lixin Zhang, John B Carter, Wilson C Hsieh, and Sally A. McKee. In the Proceedings of International Conference on Parallel Architectures and Compilation Techniques (1999), pp. 98-107, October 1999.
    Impulse: Building a Smarter Memory Controller John Carter, Wilson Hsieh, Leigh Stoller, Mark Swanson, Lixin Zhang, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravi Kuramkote, Mike Parker, Lambert Schaelicke, and Tera Tateyama. In the Proceedings of Fifth International Symposium on High Performance Computer Architecture, pp. 70-79, January 1999.
    Memory System Support for Irregular Applications John Carter, Wilson Hsieh, Mark Swanson, Lixin Zhang, Al Davis, Mike Parker, Lambert Schaelicke, Leigh Stoller, and Tera Tateyama. In the Fourth Workshop on Languages, Compilers, and Run-time Systems for Scalable Computers , pp. 9-14, May 1998
    Technical Reports
    Developers Manual of Mamboˇs Cycle Accurate Core Model Lixin Zhang. IBM Confidential, February, 2009.
    How to Develop Mambo Source Code James Peterson, Lixin Zhang. IBM Confidential, March, 2008.
    Reference Manual of Mamboˇs Bus Model Lixin Zhang. IBM Confidential, May, 2006
    URSIM User Manual
    Lixin Zhang. Technical report UUCS-03-011, University of Utah, March, 2003.
    Functionality of the Impulse Memory Controller Lixin Zhang. Technical report UUCS-01-009, University of Utah, July, 2001.
    URSIM Reference Manual Lixin Zhang. Technical report UUCS-00-015, University of Utah, August, 2000.
    A DRAM Backend for The Impulse Memory System Lixin Zhang. Technical report UUCS-00-002, University of Utah, January, 2000.
    A Comparison of Online Superpage Promotion Mechanisms Zhen Fang and Lixin Zhang. Technical report UUCS-99-021, University of Utah, December, 1999.
    Reference Manual of Impulse System Calls Lixin Zhang and Leigh Stoller. Technical report UUCS-99-018, University of Utah, October, 1999.
    ISIM: The Simulator for The Impulse Adaptable Memory System Lixin Zhang. Technical report UUCS-99-017, University of Utah, September, 1999.
    PROFESSIONAL SERVICES
    General Chair, The 19th International Symposium on High Performance Computer Architecture, Feb. 2013
    General Chair, ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, June 2012
    Program committee co-chair, Workshop on Large-Scale Parallel Processing, May 2012
    Program committee member, 26th IEEE International Parallel & Distributed Processing Symposium, May 2012
    Workshops and Tutorials co-Chair, The 18th International Symposium on High Performance Computer Architecture, Feb., 2012
    Program committee member, IEEE International Conference on Supercomputing, 2011
    Program committee member, IEEE Asia-Pacific Services Computing Conference (IEEE APSCC), 2008, 2009
    Program Committee member, 3rd International Symposium on Trustworthiness, Reliability and services in Ubiquitous and Sensor neTworks (TRUST-08), Dec. 2008
    International Editorial Board, Special Issue of AutoSoft Journal ¨Applications and Security Services in Web and Pervasive environments〃, 2008
    Program Committee, Wuhan International Conference on E-Business, 2008, 2009
    Financial chair, International Symposium on high performance computer architecture (HPCAˇ08), Feb 2008
    Program committee member, The 2007 Asia-Pacific Services Computing Conference (APSCC-07), December 2007
    Program committee member, International Conference on high performance computing, networking and storage (SC07), November 2007
    Program committee member, International Conference on Network and Parallel Computing, 2007, 2011
    Program committee member, Workshop on the Interaction between Operating Systems and Computer Architecture, June 2007
    Financial chair, International Conference on Parallel Architectures and Compilation Techniques, September 2006
    Program committee member, International Conference on Parallel Processing, August 2006
    Program committee member, IBM 7th Annual Austin Center for Advanced Studies Conference, February 2006
    Co-chair, program committee member, Workshop on Memory Performance Issues, February 2006
    Session chair, IEEE International Symposium on Workload Characterization, October 2005
    Program committee member, International Conference on Network and Parallel Computing, November 2005
    Program committee member, IBM 6th Annual Austin Center for Advanced Studies Conference, February 2005
    Co-chair, program committee member, Workshop on Memory Performance Issues, June 2004
    Panelist, NSF Computer System Architecture Review Panel, May 2004
    Submission chair, International Conference on Parallel Architectures and Compilation Techniques, September 2003
    Session chair, International Conference on Parallel Architectures and Compilation Techniques, September 2002
    Web chair, International Conference on Parallel Architectures and Compilation Techniques, September 2002
    PROFESSIONAL MEMBERSHIPS
    Senior Member of ACM
    Senior Member of IEEE
    AWARDS
    IBM, Master Inventor, 2009
    IBM, Equity Award, ¨To recognize your critical contribution to IBMˇs success〃, Nov. 2009
    IBM, Bravo Award, ¨Assistance with SMT tracing for P7 verification〃, July. 2008
    IBM, Outstanding Technical Achievement Award, ¨Demonstration of IBM's Leadership in HPC through PERCS〃, Mar. 2008
    IBM, Bravo Award, ¨Contributions to closing the NCSA deal and the supporting performance work〃, Nov. 2007
    IBM, Retention Award, ¨In recognition of your skills and anticipated contributions and your critical role〃, July, 2007
    IBM, Outstanding Technical Achievement Award, ¨Core Contributions to the success of the Mambo Full System Simulator〃, Jan. 2007
    IBM, Bravo Award, ¨Delivering the force behind: PlayStation 3〃, Dec. 2006
    IBM, Research Division Technical Group Award for ¨Contributions to the success of PERCS Milestone 6〃, March, 2006
    IBM, Research Division Team Group Award for ¨Delivery of IBMˇs Full System Simulator for Cell Broadband Engine as part of the Cell SDK 1.0 Global Release〃, December, 2005
    IBM, Research Division Technical Group Award for ¨IBM Full System Simulator (Mambo) Public Cell Release and Impact on Xbox 360 Product Release〃, December, 2005
    IBM, Invention Achievement Award, February, 2005
    Graduate Research Supplement Award, University of Utah, June, 2000
    Conference Travel Grant: HPCA-2001, ASPLOS-2000, PACT-99, and HPCA-99
    Excellent Graduate Award, Fudan University, July, 1993
    People's Scholarship, Fudan University, every semester during 09/1989 -- 07/1993
    PATENTS (Granted)
    1. US8386690, IBM AUS920090226US1, ¨On-chip Networks For Flexible Three-Dimensional Chip Integration〃, Jian Li, Lixin Zhang
    2. US8358503, ¨Stackable Module For Energy-Efficient Computing Systems〃, John Carter, Wael El-Essawy, Mootaz Elnozahy, M.K. Iyengar, Wesley Felter, Tom Keller, Juan Rubio, Kathick Rajamani, Evan Speight, Lixin Zhang
    3. US8346988, ¨Technique for Dynamically Sharing A Fabric To Facilitate Off-chip Communication〃, Jian Li, Even Speight, Lixin Zhang
    4. US8341355, ¨Reducing Energy Consumption of Set Associative Caches by Reducing Checked Ways of The Set Association〃, Jian Li, Even Speight, Lixin Zhang
    5. US8310936, "Link services in a communication network", Jian Li, Lixin Zhang
    6. US8285973, "Utilization of branch predictability in thread scheduling", Wael El-Essawy, Lixin Zhang
    7. US8271729, ¨Read and Write Aware Cache〃, Jian Li, Ram Rajamony, Evan Speight, Lixin Zhang
    8. US8266381, "Data processing system, processor and method for varying a data prefetch size based upon data usage", Ravi Arimilli, Calin Cascaval, William Speight, Balaram Sinharoy, Lixin Zhang
    9. US8255631, "System and method for priority based prefetch requests scheduling and throttling", Lei Chen, Lixin Zhang
    10. US8250307, "Method and system for sourcing differing amounts of prefetch data in response to data prefetch requests", Ravi Arimilli, Calin Cascaval, William Speight, Balaram Sinharoy, Lixin Zhang
    11. US8250298, ¨Mechanisms for Reducing DRAM Power Consumption〃, Mootaz Elnozahy, Kathick Rajamani, Evan Speight, Lixin Zhang
    12. US8209488, "Techniques for prediction based indirect data prefetching", Ravi Arimilli, William Speight, Balaram Sinharoy, Lixin Zhang
    13. US8179674, "Scalable space-optimized and energy-efficient computing system", John Carter, Wael El-Essawy, Mootaz Elnozahy, M.K. Iyengar, Tom Keller, Jian Li, Juan Rubio, Kathick Rajamani, Evan Speight, Lixin Zhang
    14. US8166277, "Data prefetching using indirect addressing", Ravi Arimilli, Balaram Sinharoy, William Speight, Lixin Zhang
    15. US8161265, "Techniques for multi-level indirect data prefetching", Ravi Arimilli, Balaram Sinharoy, William Speight, Lixin Zhang
    16. US8161264, "Techniques for data prefetching using indirect addressing with offset", Ravi Arimilli, Balaram Sinharoy, William Speight, Lixin Zhang
    17. US8161263, "Techniques for indirect data prefetching", Ravi Arimilli, Balaram Sinharoy, William Speight, Lixin Zhang
    18. US8140768, "Jump starting prefetch streams across page boundaries", William Speight, Lixin Zhang
    19. US8086831, "Indexed table circuit having reduced aliasing", Lei Chen, Lixin Zhang
    20. US7546417, "Method and system for reducing cache tag bits", Ram Rajamony, William Speight, Lixin Zhang
    21. US7886132, "Predication support in an out of order processor by selectively executing ambiguously renamed write operations", Ram Rangan, Mark Stephenson, Lixin Zhang
    22. US7958317, "A cache-based sequential prefetch engine", William Speight, Lixin Zhang
    23. US7958316, "Dynamic adjustment of prefetch stream priority", William Speight, Lixin Zhang
    24. US7962722, "Data processing system, processor and method of data processing having branch target address cache with hashed indices", Sheldon Levenstein, David Levitan, Lixin Zhang
    25. US7865705, "Data processing system, processor and method of data processing having branch target address cache including address type tag bit", David Levitan, Lixin Zhang
    26. US7877586, "Data processing system, processor and method of data processing having branch target address cache selectively applying a delayed hit", David Levitan, Lixin Zhang
    27. US7844807, "Data processing system, processor and method of data processing having branch target address cache storing direct predictions", David Levitan, Lixin Zhang
    28. US7783870, "Branch target address cache", David Levitan, William Speight, Lixin Zhang
    29. US7707396, "Data processing system, processor and method of data processing having improved branch target address cache", Jeffrey Bradford, Rick Doing, Wael El-Essawy, Rick Eickemeyer, Doug Logan, William Speight, Balaram Sinharoy, Lixin Zhang
    30. (い.)ZL200710192759.4
    31. US7506119, "Compiler assisted victim cache bypassing", Yaoqing Gao, William Speight, Lixin Zhang
    US7761673, "Compiler assisted victim cache bypassing", Yaoqing Gao, William Speight, Lixin Zhang (Duplicates?)
    32. US7657729, "An efficient multiple-table reference prediction mechanism", Wael El-Essawy, Ram Rajamony, Hazim Shafi, William Speight, Lixin Zhang
    33. US7487297, "Just-in-time prefetching", Wael El-Essawy, Ram Rajamony, Hazim Shafi, William Speight, Lixin Zhang
    34. US7698508, "System and method for reducing unnecessary cache operations", Ram Rajamony, Hazim Shafi, William Speight, Lixin Zhang
    35. US7281092: System and method of managing cache hierarchies with adaptive mechanisms, William E Speight, Hazim Shafi, Ram Rajamony, Lixin Zhang
    36. US7181589: System and method for performing address translation in a computer system, Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, John Carter, Lixin Zhang, Michael Parker
    37. US7464115, Node Synchronization for Multi-Processor Computer Systems, John Carter, Randal S. Passint, Donglai Dai, Zhen Fang, Lixin Zhang, Gregory M. Thorson,
    PATENTS (Filed)
    38. US 20100115204, ¨Non-Uniform Cache Architecture (NUCA)〃, Jian Li, Ram Rajamony, Even Speight, Xiaoxia Wu, Lixin Zhang
    39. IBM AUS920100221US1, ¨Fast Remote Communication and Computation Between Processors〃, John Carter, Mootaz Elnozahy, Ahmed Gheith, Karthick Rajamani, Evan Speight, Lixin Zhang
    40. IBM AUS920100220US1, ¨Register Allocation To Threads〃, Freeman Rawson, Even Speight, Lixin Zhang
    41. IBM AUS920100205US1, ¨Latency Tolerant 3D On-chip Memory Organization〃, Jian Li, Even Speight, Lixin Zhang
    42. IBM AUS920100206US1, ¨Assigning Memory To On-Chip Coherence Domains〃, Jian Li, Even Speight, Lixin Zhang
    43. IBM AUS920100208US1, ¨Scalable Space-Optimized And Energy Efficient Computing Systems〃, John Carter, Wael El-Essawy, Mootaz Elnozahy, M.K. Iyengar, Tom Keller, Jian Li, Juan Rubio, Kathick Rajamani, Evan Speight, Lixin Zhang
    44. IBM AUS920100211US1, ¨Instruction Set Architecture Extensions for Performing Power vs. Performance〃, John Carter, Jian Li, Kathick Rajamani, Evan Speight, Lixin Zhang
    45. IBM AUS920080508US1, ¨Fine-grained Cache Allocation〃, Ram Rajamony, Evan Speight, Lixin Zhang
    46. IBM AUS920070584US1,, "Data processing system, processor and method of data processing having improved branch target address cache", David Levitan, William Speight, Lixin Zhang
    47. IBM AUS920090082US1, ¨Fine-grained Cache Allocation〃, Ram Rajamony, Evan Speight, Lixin Zhang
    48. IBM AUS920090085US1, ¨Cache Partitioning in Virtualized Environments〃, Jiang Lin, Lixin Zhang
    49. IBM AUS920080732US1, ¨Method And System For Performance Isolation In Virtualized Environments〃, Elmootazbellah N. Elnozahy, Ram Rajamony, Evan Speight, Lixin Zhang
    50. IBM , YOR820090116, ¨Prefetch instructions with target memory hierarchy specified for multi-core system〃, Yaoqing Gao, Zehra Sura, John OˇBrien, Lixin Zhang
    51. IBM AUS920080508US1, ¨Method And System For Efficient Data Organizations Using Intermediate Addresses〃, Ram Rajamony, Evan Speight, Lixin Zhang
    52. IBM CA920060047US1, "Software solution for cooperative memory-side and processor-side data prefetching", Calin Cascaval, Yaoqing Gao, Allen Kielstra, Robert Tremaine, Michael Wazlowski, Lixin Zhang
    53. IBM CA920050056US1, "Method and apparatus for software-assisted data cache and prefetch control", Roch Archambault, Yaoqing Gao, Frank O'Connell, Robert Tremaine, Mike Wazlowski, Steve White, Lixin Zhang
    54. IBM AUS920080373US1, "Predication supporting code generation by indicating path association s of symmetrically placed write instructions", Ram Rangan, Mark Stephenson, Lixin Zhang
    55. IBM AUS820080376, "Software mechanisms for power-aware on-demand interconnect link services", Jian Li, Lixin Zhang
    56. IBM AUS920071055US1, "Data processing system, processor and method that support a touch of a partial cache line of data", Ravi Arimilli, Calin Cascaval, William Speight, Balaram Sinharoy, Lixin Zhang
    57. IBM AUS920071054US1, "Data processing system, processing and method that vary an amount of data retrieved from memory based upon a hint", Ravi Arimilli, Calin Cascaval, William Speight, Balaram Sinharoy, Lixin Zhang
    58. IBM AUS920070583US1, "Techniques for predicated execution in an out of order processor", Ram Rangan, William Speight, Mark Stephenson, Lixin Zhang
    59. IBM AUS920070835US1, "Method, system and program product for address translation through an intermediate address space", Ram Rajamony, William Speight, Lixin Zhang
    60. IBM AUS920060340US1, "Branch target extension for instruction cache", Lei Chen, Hu Zhigang, Lixin Zhang
    61. IBM AUS920060194US1, "Data processing system and method for reducing cache pollution by write stream memory access patterns", Ravi Arimilli, Frank O'Connell, Hazim Shafi, Derek Williams, Lixin Zhang
    62. SGI: Serial number 60/676.551, Directory Delegation and Update Pushing in Shared Memory Microprocessor Systems, John Carter, Randal S. Passint, Lixin Zhang, Donglai Dai,

     

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