Annual Highlights
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The Research of SKLP has been Nominated for the Best Paper in ICCAD 2024Recently, the paperDDP-Fsim:Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelismfrom the State Key Lab of Processors was nominated as a Best Paper Award Candidate at ICCAD 2024. Recently, the paper “DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism” from the State Key Lab of Processors was nominated as a Best Paper Award Candidate at ICCAD 2024, a CCF-recommended Category B international conference. The first author of the paper is Master’s student Gu Feng (supervised by Associate Researcher Ye Jing).As sem... -
Students and Faculty from the State Key Lab of Processors Won the Best Paper Award of the 32nd IEEE ATSRecently, Wenxing Li, a Ph.D. student at the State Key Lab of Processors (SKLP), Institute of Computing Technology, Chinese Academy of Sciences (supervised by Professor Huawei Li), was awarded the sole Best Paper Award of the 32nd IEEE ATS, at the opening ceremony of ATS 2024 (held in Ahmedabad, India), for the paper titled Intelligent Automatic Test Pattern Generation for Digital Circuits Ba... Recently, Wenxing Li, a Ph.D. student at the State Key Lab of Processors (SKLP), Institute of Computing Technology, Chinese Academy of Sciences (supervised by Professor Huawei Li), was awarded the sole Best Paper Award of the 32nd IEEE ATS, at the opening ceremony of ATS 2024 (held in Ahmedabad, India), for the paper titled Intelligent Automatic Test Pattern Generation for Digital Circuits Base... -
Four Papers of State Key Laboratory of Processors were Accepted by MICRO 2024Four papers titled "Cambricon-LLM: A Chiplet-Based Hybrid Architecture for On-Device Inference of 70B LLM", "Cambricon-M: a Fibonacci-coded Charge-domain SRAM-based CIM Accelerator for DNN Inference", "Cambricon-C: Efficient 4-bit Matrix Unit via Primitivization", and "TMiner: A Vertex-Based Task Scheduling Architecture for Graph Pattern Mining", authored by researchers from the State Key Labor... Four papers titled "Cambricon-LLM: A Chiplet-Based Hybrid Architecture for On-Device Inference of 70B LLM", "Cambricon-M: a Fibonacci-coded Charge-domain SRAM-based CIM Accelerator for DNN Inference", "Cambricon-C: Efficient 4-bit Matrix Unit via Primitivization", and "TMiner: A Vertex-Based Task Scheduling Architecture for Graph Pattern Mining", authored by researchers from the State Key Labor... -
Students and Faculty from Key Laboratory of AI Safety, Chinese Academy of Sciences won EMNLP 2024 Best Paper AwardRecently, Weichao Zhang, a Ph.D. student at the Key Laboratory of AI Safety, Chinese Academy of Sciences (supervised by Professor Jiafeng Guo), was awarded the Best Paper Award at the EMNLP 2024 conference for paper titled Pretraining Data Detection for Large Language Models: A Divergence-based Calibration Method, in which he is the first author.The 2024 Conference on Empirical Methods in Natur... -
18 Papers of Key Laboratory of Intelligent Al Safety (Chinese Academy of Sciences) were Accepted by ACL 2024
The Annual Meeting of the Association for Computational Linguistics (ACL) is the top ranked international academic conference in the fields of computational linguistics and natural language processing. It is organized by the International Association for Computational Linguistics and held annually. ACL is listed as an A-class conference in the recommended conference list of the Chinese Computer... The Annual Meeting of the Association for Computational Linguistics (ACL) is the top ranked international academic conference in the fields of computational linguistics and natural language processing. It is organized by the International Association for Computational Linguistics and held annually. ACL is listed as an A-class conference in the recommended conference list of the Chinese Computer... -
Breakthroughs in the State Key Laboratory of Processors :Automated Processor DesignProcessor design is a highly challenging and labor-intensive task. In conventional CPU design flow, a team of talented engineers uses formal programming languages (e.g., Verilog, Chisel, or C/C++) to implement the circuit logic of a CPU based on design specifications. Then billions of dedicated test cases with both inputs and their expected outputs are developed to test the functionality of th... Processor design is a highly challenging and labor-intensive task. In conventional CPU design flow, a team of talented engineers uses formal programming languages (e.g., Verilog, Chisel, or C/C++) to implement the circuit logic of a CPU based on design specifications. Then billions of dedicated test cases with both inputs and their expected outputs are developed to test the functionality of th...