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Storage and Computing Integrated Chip EDA Toolchain
They successfully deployed a MoE large model, achieving an order of magnitude increase in throughputcompared to manual deployment.
The Intelligent Computer Research Center has developed an integrated memory-computing chip. The EDA toolchain is the first open-source integrated memory-computing hardware and software collaborative design toolchain in the world, breaking through the difficulties of automatic architecture generation and automatic algorithm deployment, supporting neural network acceleration and energy efficiency...
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Centering Around the New-generation Intelligent System, Its Influence in the Fields of AI + Life and Health and AI + Agriculture is Constantly Increasing.
In the aspect of medical and health, as a pivotal member of an interdisciplinary research consortium, we contributed to the development and publication of GeneCompass, a groundbreaking knowledge-informed cross-species gene foundation model.
In the aspect of medical and health, as a pivotal member of an interdisciplinary research consortium, we contributed to the development and publication of GeneCompass, a groundbreaking knowledge-informed cross-species gene foundation model. This innovative model has demonstrated remarkable potential in enhancing the efficiency of target gene identification through the seamless integration of in...
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Key Technological Breakthroughs in the Construction of the “Model Federated Network (MoFedNet)” Platform
The Ubiquitous Technology Research Center has made a breakthrough in large-scale heterogeneous data fusion technology for models without training, constructing the FedBone framework, achieving an optimized balance of utility, privacy, and fairness.
The Ubiquitous Technology Research Center has made a breakthrough in large-scale heterogeneous data fusion technology for models without training, constructing the FedBone framework, achieving an optimized balance of utility, privacy, and fairness, and implementing the digital ophthalmology federated collaboration platform (FedEYE).FedBone “links” the large model construction framework, enabl...
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Loongson 3C6000 Server CPU
The dual-die Loongson 3D6000, equipped with 8 channels of 72-bit DDR4-3200 memory, achieves performance on par with Intels Xeon Gold 6338.
The Loongson 3C6000 server CPU, jointly developed by the Microprocessor Research Center of Institute of Computing Technology, Chinese Academy of Sciences and Loongson Technology Co., Ltd, is based on the LoongArch instruction set architecture and manufactured using 12nm process. With a main frequency of 2.2 GHz, it achieves a peak performance of 844.8 GFLOPs with double-precision floating-point...
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The Research of SKLP has been Nominated for the Best Paper in ICCAD 2024
Recently, the paperDDP-Fsim:Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelismfrom the State Key Lab of Processors was nominated as a Best Paper Award Candidate at ICCAD 2024.
Recently, the paper “DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism” from the State Key Lab of Processors was nominated as a Best Paper Award Candidate at ICCAD 2024, a CCF-recommended Category B international conference. The first author of the paper is Master’s student Gu Feng (supervised by Associate Researcher Ye Jing).As sem...
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Students and Faculty from the State Key Lab of Processors Won the Best Paper Award of the 32nd IEEE ATS
Recently, Wenxing Li, a Ph.D. student at the State Key Lab of Processors (SKLP), Institute of Computing Technology, Chinese Academy of Sciences (supervised by Professor Huawei Li), was awarded the sole Best Paper Award of the 32nd IEEE ATS, at the opening ceremony of ATS 2024 (held in Ahmedabad, India), for the paper titled Intelligent Automatic Test Pattern Generation for Digital Circuits Ba...
Recently, Wenxing Li, a Ph.D. student at the State Key Lab of Processors (SKLP), Institute of Computing Technology, Chinese Academy of Sciences (supervised by Professor Huawei Li), was awarded the sole Best Paper Award of the 32nd IEEE ATS, at the opening ceremony of ATS 2024 (held in Ahmedabad, India), for the paper titled Intelligent Automatic Test Pattern Generation for Digital Circuits Base...