On Aug. 25, 2011, Professor Yiran Chen from University of Pittsburgh visited State Key Laboratory of Computer Architecture and gave a talk.
Prof. Chen gave a talk titled The applications of STT-RAM in Microarchitecture.As device dimensions shrink into the nanometer regime, most of the current dominant memory technologies, e.g., SRAM, DRAM and Flash, arefacing severe scalability challenges. Many emerging memory technologies, e.g., Spin-Transfer Torque Memory (STT-RAM) demonstrated many attractive characteristics: high-density, high-speed access, zero standby power,non-volatility, unlimited endurance and CMOS integration compatibility. The adoption of these new technologies will dramatically change the landscape of modern computing system designs. This talk was based on his works in ISLPED2011 and MICRO 2011, respectively. In the first part he studies the use of multi-level STT-RAM cells in the design of processor caches and offers solutions to the issue of bit encoding as well as tackle the write endurance problem. He also proposes a set remapping scheme that can potentially prolong the lifetime of a MLC STT-RAM cache by 80X on average. Furthermore, a method for recovering the performance that may be lost in some applications due to set remapping is introduced.
After the talk, Prof. Chen and Yinhe Han’team members discussed some interesting research ideas and agreed to keep a long-term cooperation with each other.
Prof. Chen received B.S. and M.S. in EE from Tsinghua University, China and Ph.D. in ECE from Purdue University, W. Lafayette, IN. Before he joined University of Pittsburgh in 2010, he worked with Synopsys and Seagate for five years. Dr. Chen‘s research interests include VLSI design, computer architecture, nueromorphic computing, and emerging electronic devices,memory and sensors. He has published more than 80 technical publications, has 37 granted US patents and the other 28 pending applications.
downloadFile