Recently, the OFDM technology has been adopted in various high bandwidth wireless standards, such as Mobile WiMAX, 3GPP LTE and LTE-Advanced. The implementation of the FFT processing in these standards is not easy. The processor for FFT implementation need to meet some critical requirements, for example, high throughput, easy reprogram to support different standards; and satisfying energy and area budgets. Based on an analysis of recent researches, ASIP in general can better meet these requirements.
We proposed an Application Specific Instruction Set Processor (ASIP) pruned for high-throughput and variable-length Fast Fourier Transform (FFT), which is a key component of various Orthogonal Frequency Division Multiplexing (OFDM)-based wireless communication standards. The ASIP executes dedicated FFT instructions to process two radix-4 or four radix-2 butterfly operations every clock cycle. Furthermore, a shuffle-embedded register file and a programmable memory access coprocessor are employed to tackle the memory access bottleneck and reduce power consumption. The implementation results show that our ASIP requires only 892 clock cycles for a 1024-point FFT, which outperforms TI TMS320C64x DSP and Tensilica ConnX ASIP by 6.74X and 2.03X, respectively. A test chip of the proposed ASIP was fabricated using CMOS 65nm process with the core area of 1.9mm2. It consumes 85mW when it runs at the maximum frequency of 150MHz.
This research entitled " An Application Specific Instruction Set Processor Optimized for FFT" has been accepted by the 54th International Midwest Symposium on Circuits and Systems (IEEE MWSCAS 2011).
We proposed an Application Specific Instruction Set Processor (ASIP) pruned for high-throughput and variable-length Fast Fourier Transform (FFT), which is a key component of various Orthogonal Frequency Division Multiplexing (OFDM)-based wireless communication standards. The ASIP executes dedicated FFT instructions to process two radix-4 or four radix-2 butterfly operations every clock cycle. Furthermore, a shuffle-embedded register file and a programmable memory access coprocessor are employed to tackle the memory access bottleneck and reduce power consumption. The implementation results show that our ASIP requires only 892 clock cycles for a 1024-point FFT, which outperforms TI TMS320C64x DSP and Tensilica ConnX ASIP by 6.74X and 2.03X, respectively. A test chip of the proposed ASIP was fabricated using CMOS 65nm process with the core area of 1.9mm2. It consumes 85mW when it runs at the maximum frequency of 150MHz.
This research entitled " An Application Specific Instruction Set Processor Optimized for FFT" has been accepted by the 54th International Midwest Symposium on Circuits and Systems (IEEE MWSCAS 2011).
downloadFile